**Pierpaolo Palestri **received the Laurea degree in Electronic Engineering (cum laude) from the University of Bologna, Italy, in 1998 with a thesis on impact ionization in bipolar transistors. From 1998 to 2000, he received a research grant from the University of Udine, Italy, where he worked on the simulation and optimization of bipolar transistors and on the analysis of hot electron phenomena in MOS devices and non-volatile memories. From July 2000 to October 2001 he was a Post-Doctoral Member of Technical Staff at Bell Labs (Lucent Technology, Murray Hill, New Jersey), working on the simulation and experimental characterization of silicon-germanium bipolars.

In November 2001, he became Assistant Professor at the University of Udine, where he then finished his PhD in 2003. Since November 2005, he has been Associate Professor of Electronics at the University of Udine. P.Palestri has been responsible for the University of Udine of EU and national projects as well as contracts with semiconductor companies for a total amount of approximately 1Meuros.

The scientific activity of P.Palestri has been mainly focused on the development of sophisticated modeling tools for electron devices (bipolars, MOSFETs, non-volatile memories, sensors). These activities have been carried out in collaboration with colleagues at the University of in the framework of many European and national projects as well as in collaboration with many companies, among them Lucent Technologies USA, Philips Eindhoven and NXP Leuven, TSMC Taiwan/ TSMC Europe, STMicroelectronics Crolles. In most cases, the modeling activities have been complemented by extensive experimental characterization. In the framework of a long standing collaboration between the University of Udine and Infineon Technologies P.Palestri has been involved in the modeling and design of basic building block for RF systems (phase-locked-loops, low-noise-amplifiers, voltage-controlled-oscillators, frequency dividers) and interfaces for high-speed serial communication. The research activities resulted in approximately 300 papers in international journals with peer-review and international conferences with peer-review, 8 chapters in edited books and one book. He tutored 10 PhD students at the university of Udine and has been the co-tutor of many other PhD students at the University of Udine as well as at the University of Calabria, University of Modena-Reggio Emilia and at the École Polytechnique Fédérale de Lausanne.

P.Palestri has been the organizer (with colleagues L.Selmi, D.Esseni and Driussi) of the conferences ULIS 2003, ULIS 2008, GE 2013 INFOS 2015, SISPAD 2019 and EUROSOI-ULIS 2022, all held in Udine

Pierpaolo Palestri is a senior member of the IEEE.

**Selected paublications.**

**P. Palestri**, D. Esseni, S. Eminente, C. Fiegna, E. Sangiorgi, L. Selmi, "Understanding Quasi-Ballistic Transport in nano-MOSFETs. Part I: Scattering in the Channel and in the Drain", pp. 2727-2735, IEEE Transactions on Electron Devices, vol. 52, n. 12, December 2005

R. Nonis, N. Da Dalt, **P. Palestri**, L. Selmi, "Modeling, design and characterization of a new Low Jitter analog Dual Tuning LC-VCO PLL Architecture", pp. 1303-1309, IEEE Journal of Solid State Circuits, vol. 40, n. 6, June 2005

M. Lenzi, **P. Palestri**, E. Gnani, S. Reggiani, A. Gnudi, D. Esseni, L. Selmi, G. Baccarani, "Investigation of the transport properties of silicon nanowires using deterministic and Monte Carlo approaches to the solution of the Boltzmann Transport Equation" pp. 2086-2096, IEEE Transactions on Electron Devices, vol. 55, n. 8, August 2008

M. Bresciani, **P. Palestri**, D. Esseni, L. Selmi, "Simple and efficient modeling of the E-k relationship and low-field mobility in Graphene Nano-Ribbons", pp. 1015-1021, Solid State Electronics, vol. 54, n. 9, September 2010

A. Bandiziol, **P. Palestri**, F. Pittino, D. Esseni, L. Selmi, "TCAD-Based Methodology to Model the Site-Binding Charge at ISFET/Electrolyte Interfaces", pp. 3379-3386, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 62, n. 10, October 2015;

S. Strangio, **P. Palestri**, M. Lanuzza, F. Crupi, D. Esseni, L. Selmi, "Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits", pp. 2749-2756, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, n. 7 July 2016

C. Nichetti, A. Pilotto, **P. Palestri**, L. Selmi, M. Antonelli, F. Arfelli, G. Biasiol, G. Cautero, F. Driussi, N. Y. Klein, R. H. Menk, T. Steinhartova, "An Improved Nonlocal History-Dependent Model for Gain and Noise in Avalanche Photodiodes Based on Energy Balance Equation", pp.1823-1829, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.65, n.5, May 2018

L. J. Mele, **P. Palestri**, L. Selmi, "General Approach to Model the Surface Charge Induced by Multiple Surface Chemical Reactions in Potentiometric FET Sensors", pp.1149-1156 IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 67, n. 3, March 2020

R. Asanovski, **P. Palestri**, L. Selmi, “Importance of charge trapping/detrapping involving the gate electrode on the noise currents of scaled MOSFETs”, IEEE Transactions on Electron Devices, vol. 69, n.3, pp. 1313-1320, March 2022

Dipartimento Politecnico di Ingegneria e Architettura

Via delle Scienze 206, 33100 Udine - Italy

tel. +39 0432 558249

pierpaolo.palestri(at)uniud.it

### A few selected publications

**P. Palestri**, D. Esseni, S. Eminente, C. Fiegna, E. Sangiorgi, L. Selmi, "Understanding Quasi-Ballistic Transport in nano-MOSFETs. Part I: Scattering in the Channel and in the Drain", pp. 2727-2735, IEEE Transactions on Electron Devices, vol. 52, n. 12, December 2005

R. Nonis, N. Da Dalt, **P. Palestri**, L. Selmi, "Modeling, design and characterization of a new Low Jitter analog Dual Tuning LC-VCO PLL Architecture", pp. 1303-1309, IEEE Journal of Solid State Circuits, vol. 40, n. 6, June 2005

M. Lenzi, **P. Palestri**, E. Gnani, S. Reggiani, A. Gnudi, D. Esseni, L. Selmi, G. Baccarani, "Investigation of the transport properties of silicon nanowires using deterministic and Monte Carlo approaches to the solution of the Boltzmann Transport Equation" pp. 2086-2096, IEEE Transactions on Electron Devices, vol. 55, n. 8, August 2008

M. Bresciani, **P. Palestri**, D. Esseni, L. Selmi, "Simple and efficient modeling of the E-k relationship and low-field mobility in Graphene Nano-Ribbons", pp. 1015-1021, Solid State Electronics, vol. 54, n. 9, September 2010

A. Bandiziol, **P. Palestri**, F. Pittino, D. Esseni, L. Selmi, "TCAD-Based Methodology to Model the Site-Binding Charge at ISFET/Electrolyte Interfaces", pp. 3379-3386, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 62, n. 10, October 2015;

S. Strangio, **P. Palestri**, M. Lanuzza, F. Crupi, D. Esseni, L. Selmi, "Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits", pp. 2749-2756, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, n. 7 July 2016

C. Nichetti, A. Pilotto, **P. Palestri**, L. Selmi, M. Antonelli, F. Arfelli, G. Biasiol, G. Cautero, F. Driussi, N. Y. Klein, R. H. Menk, T. Steinhartova, "An Improved Nonlocal History-Dependent Model for Gain and Noise in Avalanche Photodiodes Based on Energy Balance Equation", pp.1823-1829, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.65, n.5, May 2018

L. J. Mele, **P. Palestri**, L. Selmi, "General Approach to Model the Surface Charge Induced by Multiple Surface Chemical Reactions in Potentiometric FET Sensors", pp.1149-1156 IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 67, n. 3, March 2020

R. Asanovski, **P. Palestri**, L. Selmi, “Importance of charge trapping/detrapping involving the gate electrode on the noise currents of scaled MOSFETs”, IEEE Transactions on Electron Devices, vol. 69, n.3, pp. 1313-1320, March 2022