Beyond CMOS FETs for an ultra-low energy electronics

The scaling of the power supply is probably the most effective measure to improve energy efficiency of CMOS circuits, but the fundamental limit of 60mV/dec (at room temperature) in the sub-threshold swing of CMOS transistors is a hurdle to the threshold voltage scaling, and consequently to the scaling of the power supply. Several device concepts have been proposed and investigated to overcome the 60mV/dec limit of CMOS transistors.

In this context, our group developed device and circuit-level models to analyse the operation and support the design of CMOS transistors based on band-to-band-tunneling, typically referred to as Tunnel-FETs. Our analysis was not limited to device level, but extended also to the assessment at circuit level (both digital and analog) of the prospective advantages of Tunnel-FETs. These activities about Tunnel-FETs have been developed in the framework of two projects funded by the European Union (i.e. STEEPER (FP7,GA:257267) and E2SWITCH, GA: 619509 ), and of the FIRB project number RBFR10XQZ8 entitled ‘Novel device and circuit concepts for energy-efficient electronics’.

More recently, a similar analysis was devoted to negative-capacitance transistors (NC-FETs). Negative capacitance is a term used to describe an unusual behavior of ferroelectric materials, where a decrease of the electric field across the dielectric can result in an increase of the polarization. The exploitation of ferroelectric materials in the gate stack of CMOS FETs can thus induce a voltage gain between the semiconductor interface potential and the external gate bias, which in turn can lead to a sub-threshold swing lower than 60mV/dec (at room temperature).

Selected publications

Tunnelling based Transistors

Scaling of GaSb/InAs Vertical Nanowire Esaki Diodes Down to Sub-10-nm Diameter

Y. Shao, M. Pala, D. Esseni, J. A. del Alamo. IEEE Transactions on Electron Devices, Vol. 69, pp.2188, 2022.

A review of selected topics in physics based modeling for tunnel field-effect transistors

D. Esseni, M. Pala, P. Palestri, C. Alper, T. Rollo, Semiconductor Science and Technology, vol. 32, pp. 083005, 2017.

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

F. Settino, M. Lanuzza, S. Strangio, F. Crupi, P. Palestri, D. Esseni, L. Selmi, IEEE Transactions on Electron Devices, vol. 64, p. 2736-2743, 2017.

Essential Physics of the OFF-State Current in Nanoscale MOSFETs and Tunnel FETs

D. Esseni, M. G.Pala, T. Rollo, IEEE Transactions on Electron Devices, vol. 62, p. 3084-3091, 2015.

Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells

S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi, S. Richter, Q. Zhao, S. Mantl, IEEE Journal of the Electron Devices Society, vol. 3, p. 223-232, 2015.

Single particle transport in two-dimensional heterojunction interlayer tunneling field effect transistor

Mingda Li, David Esseni, Gregory Snider, Debdeep Jena, Huili Grace Xing, Journal of Applied Physics, vol. 115, pp.2 074508, 2014.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

L. Knoll, Q. Zhao, A.Nichau, S.Trellenkamp, S.Richter, A. Schäfer, D. Esseni, L. Selmi, K.K. Bourdelle, S. Mantl, IEEE Electron Device Letters, vol. 34, p. 813-815, 2013.

Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs - Part I: Model Description and Single Trap Analysis in Tunnel-FETs

M. G. Pala, D. Esseni,. IEEE Transactions on Electron Devices, vol. 60, p. 2795-2801, 2013.

Negative Capacitance (NC) and NC Transistors

Intrinsic Nature of Negative Capacitance in Multidomain Hf0.5Zr0.5O2-Based Ferroelectric/Dielectric Heterostructures

M. Hoffmann, M. Gui, S. Slesazeck, R. Fontanini, M. Segatto, D. Esseni, T. Mikolajick, Advanced Functional Materials, pp. 2108494 , 2022.

Macroscopic and microscopic picture of negative capacitance operation in ferroelectric capacitors

D. Esseni and R.Fontanini, Nanoscale, vol. 13, p. 9641-9650, 2021.

Stabilization of negative capacitance in ferroelectric capacitors with and without a metal interlayer

T.Rollo, F. Blanchini, G. Giordano, R. Specogna, D. Esseni, Nanoscale, 12, 6121–6129, 2020.

New design perspective for Ferroelectric NC-FETs

T.Rollo,  D. Esseni. IEEE Electron Device Lettters, Vol.39, pp.603 , 2018.

Influence of Interface Traps on Ferroelectric NC-FETs

T.Rollo,  D. Esseni. IEEE Electron Device Lettters, Vol.39, pp.1100, 2018.

Energy Minimization and Kirchhoff’s Laws in Negative Capacitance Ferroelectric Capacitors and MOSFETs

T.Rollo,  D. Esseni. IEEE Electron Device Lettters, Vol.38, pp.814, 2017.