Beyond CMOS FETs for an ultra-low energy electronics

The scaling of the power supply is probably the most effective measure to improve energy efficiency of CMOS circuits, but the fundamental limit of 60mV/dec (at room temperature) in the sub-threshold swing of CMOS transistors is a hurdle to the threshold voltage scaling, and consequently to the scaling of the power supply. Several device concepts have been proposed and investigated to overcome the 60mV/dec limit of CMOS transistors.

In this context, our group developed device and circuit-level models to analyse the operation and support the design of CMOS transistors based on band-to-band-tunneling, typically referred to as Tunnel-FETs. Our analysis was not limited to device level, but extended also to the assessment at circuit level (both digital and analog) of the prospective advantages of Tunnel-FETs. These activities about Tunnel-FETs have been developed in the framework of two projects funded by the European Union (i.e. STEEPER (FP7,GA:257267) and E2SWITCH, GA: 619509 http://www.e2switch.org/ ), and of the FIRB project number RBFR10XQZ8 entitled ‘Novel device and circuit concepts for energy-efficient electronics’.

More recently, a similar analysis was devoted to negative-capacitance transistors (NC-FETs). Negative capacitance is a term used to describe an unusual behavior of ferroelectric materials, where a decrease of the electric field across the dielectric can result in an increase of the polarization. The exploitation of ferroelectric materials in the gate stack of CMOS FETs can thus induce a voltage gain between the semiconductor interface potential and the external gate bias, which in turn can lead to a sub-threshold swing lower than 60mV/dec (at room temperature).